1. Field of the Invention
The present invention relates to a semiconductor device including a MOS (Metal Oxide Semiconductor) field effect transistor (hereinafter referred to as "MOSFET") formed on a semiconductor substrate and, more particularly, to an improvement in supplying a substrate bias voltage.
2. Description of the Background Art
Generally, a semiconductor device such as a dynamic random access memory or a static random access memory is constituted by a number of MOS transistors formed on one semiconductor substrate. Normally, the potential of the semiconductor substrate is constantly maintained in a predetermined range in such a semiconductor device.
FIG. 20 is a schematic block diagram of such a semiconductor device. Referring to FIG. 20, the semiconductor device 100 includes functional circuit (or internal circuit) 110 and a substrate bias generating circuit 120 formed on a single semiconductor substrate. The functional circuit 110 is constituted by a number of MOS transistors for implementing functions necessary for the semiconductor device 100. The substrate bias generating circuit 120 is also constituted by MOS transistors and it generates a substrate bias voltage V.sub.BB for maintaining the semiconductor substrate 1 at a predetermined negative potential.
FIG. 21 is a cross sectional view showing a portion of a cross sectional structure of a general integrated circuit device. The functional circuit 110 shown in FIG. 20 includes the sectional structure shown in FIG. 21. FIG. 21 shows, as an example, an NMOS transistor and interconnections provided in the periphery thereof. Referring to FIG. 21, the NMOS transistor includes N type impurity regions 2 and 3 serving as source and drain formed near the main surface of the semiconductor substrate 1 and a gate electrode 5. A gate dielectric thin film 4 is formed between the gate electrode 5 and the substrate 1. P type impurities of low concentration (for example 10.sup.16 to 10.sup.17 /cm.sup.3) are introduced to the silicon substrate 1 below the gate electrode 5. N type impurities of high concentration (for example, 10.sup.19 to 10.sup.21 /cm.sup.3 ) are introduced to the source region 2 and the drain region 3. Interconnection layers 22 and 23 having low resistance are connected through contact holes formed in an interlayer insulating film 24 to the gate electrode 5, the source region 2 and to the drain region 3.
In the MOS transistor formed as described above, when a positive voltage is applied to the gate electrode 5, N type carriers (electrons) are induced at an upper layer portion of the silicon substrate 1 of P.sup.31 region. More specifically, the surface of the silicon substrate 1 is inverted to N type, so that the surface of the silicon substrate 1 has the same type of conductivity as that of the source region 2 and the drain region 3. Thus it becomes possible for a current to flow between the drain region and source region. The concentration of the N type carriers induced on the surface of the silicon substrate 1 changes dependent on the voltage applied to the gate electrode 5, and therefore the amount of current flowing between the source region 2 and the drain region 3 can be controlled by the gate voltage.
In operation, when the NMOS transistor is rendered conductive, hot electrons and holes which constitute pairs are generated near the drain region 3. Most of the generated hot electrons flow to the drain region 3. Meanwhile, most of the generated holes flow to the silicon substrate 1. Thus the potential of the silicon substrate 1 rises. The rise of the potential of the silicon substrate 1 causes the following problem.
Since PN junctions are formed between the P type silicon substrate 1 and the source region 2 and between the substrate 1 and the drain region 3, the PN junctions are brought to the forward bias state. Accordingly, leak current flows between the silicon substrate 1 and the source region 2 and the drain region 3. Consequently, there is a possibility that the channel is not formed between the source region 2 and the drain region 3, or that the signal to be transmitted is delayed.
In order to prevent the above problem, the substrate bias generating circuit 120 for keeping the potential V.sub.BB of the substrate 1 at about -1 V, for example, is provided.
The conventional operation for supplying substrate bias will be described with reference to FIG. 22. FIG. 22 shows the threshold voltages and the drivability of supplying current when the substrate bias potential is set at -1 V. Referring to FIG. 22, the solid lines represent the threshold voltage and the drivability of supplying current when the substrate bias potential is at -1 V. In the figure, (a) represents the substrate bias potential, (b) represents the threshold voltages of the NMOS transistor and (c) represents the drivability of supplying current of the NMOS transistor.
A constant substrate bias is applied (in FIG. 22, -1 V) to the silicon substrate 1 no matter whether it is in an active state or in a standby state. The threshold voltage changes in the negative direction when the substrate bias changes in the positive direction. By the change of the threshold voltage, the drivability of supplying current also changes. In the NMOS transistor, when the threshold voltage changes in the negative direction, the drivability of supplying current increases, while in a PMOS transistor, when the threshold voltage changes in the positive direction, the drivability of supplying current increases. However, in the conventional method of supplying the substrate bias, a constant substrate bias is applied, and therefore the threshold voltage and the current supplying drivability do not change as shown in FIG. 22.
Since the conventional semiconductor device is structured as described above, when the threshold voltage is set to minimize the leak current in the standby state, the drivability of supplying current at the active state becomes small, which prevents high speed operation.
Conversely, if the drivability of supplying current is increased and the threshold value is lowered in order to operate the NMOS transistor at high speed, the leak current in the standby state increases.
Now, Japanese Patent Laying-Open No. 3-29183 discloses a semiconductor memory device in which substrate potential is switched between an active state and a standby state and in which a deeper substrate bias voltage is applied at the standby state than at the active state.
FIG. 23 is a block diagram showing the device for switching the substrate bias disclosed in the aforementioned published Japanese Patent Application. Referring to FIG. 23, this device includes an identifying circuit 101 for identifying the active mode and the standby mode; a substrate potential generating circuit 103 having large current drivability for generating a second substrate potential at the active state; a substrate potential generating circuit 102 having smaller current drivability for generating a first substrate potential causing deeper reverse bias than the second substrate potential at the standby state; a comparing circuit 105 for comparing the substrate potential and a reference potential corresponding to the second substrate potential; a comparing circuit 104 for comparing the substrate potential with a reference potential corresponding to the first substrate potential; and a control portion 106 for selecting one of the substrate potential generating circuits 102 and 103 in response to an output signal from the identifying circuit 101 and maintaining constant the substrate potential generated by the selected substrate potential generating circuit in response to output signals from the comparing circuits 104 and 105.
The current drivability of the substrate potential generating circuit 102 is smaller than that of the circuit 103, since, at the standby state, the first substrate potential is generated only to prevent dissipation of the data stored in the memory cell. However, since the current drivability is small, there is a possibility that the PN junction is set to the forward biased state by the external noise. In order to prevent the forward biased state, the first substrate potential is set to a potential providing deep reverse bias.
In this prior art, the second substrate potential is made to provide shallower bias than the first substrate potential, since at the active state, there is an internal signal (for example, word lines of the memory) which is raised to be higher than the supply voltage and when the same reverse bias as the first substrate potential is applied, there is a possibility that the breakdown voltage of the PN junction is exceeded.
In operation, when a signal designating the active mode is input externally, identifying circuit 101 recognizes that it is the active mode, and allows control portion 106 control in a manner corresponding to the active mode. Control portion 106 to controls the substrate potential generating circuit 103 in response to the output from comparing circuit 105 and maintains the voltage of the substrate at the second substrate potential.
Meanwhile, when a signal designating the standby mode is input externally, identifying circuit 101 recognizes that it is the standby mode, and let the control portion 106 control in the manner corresponding to the standby mode. Control portion 106 controls substrate potential generating circuit 102 in response to the output from comparing circuit 104 and maintains the substrate potential at the first substrate potential. By doing so, the reverse bias at the standby state can be made deeper than the reverse bias at the active state, and therefore dissipation of data stored in the memory cell in the standby state can be prevented.
FIG. 24 is a graph showing an example of the relation between the supply voltage Vcc and the first and second substrate potentials b and a generated by the device shown in FIG. 23. As is apparent from FIG. 24, when the supply voltage Vcc is at 5 V, the first substrate potential b is -4 V and the second substrate potential a is -3 V. The voltage (-3 V) of the second substrate potential is similar to the substrate potential of the conventional general semiconductor device, and it is determined based on the relation with respect to the impurity concentration doped in the substrate.
Therefore, the speed of operation of the semiconductor device is approximately the same as that in the conventional general semiconductor device, and therefore, the speed of operation of the transistor can not be expected to be faster in the active state.
In order to increase the speed of operation of the semiconductor memory device, it is necessary to determine the voltage of the substrate potential taking into consideration the current drivability and the threshold voltage of the MOS transistor internally provided. Further, it is necessary to determine the first substrate potential taking into consideration the relation between the threshold voltage and the current drivability.
The prior art shown in FIG. 23 is silent about these relations.